Equivalence Checking of Loops before and after Pipelining by Applying Symbolic Simulation and Induction
نویسندگان
چکیده
When applications contain large loops, high level synthesis often takes advantage of software pipelining technique in order to improve the performance. High level synthesis with pipelining utilization needs complicated algorithms. So it is desired to check its correctness. In this paper, we propose a novel approach for equivalence checking of loops before and after pipelining. The proposed approach applies a combination of symbolic simulation technique and induction method. We develop a prototype equivalence checker based on the approach. The experimental results show that our proposed method can verify the equivalence of loops before and after pipelining.
منابع مشابه
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation
We propose a novel procedure based on uninterpreted symbolic simulation for checking the scheduling step in high-level synthesis. The primary task in scheduling is the assignment of time steps or, equivalently, states to operations. Various transformations like operation reordering and loop unrolling may be performed in the process to meet the optimization criteria. The contribution of our prop...
متن کاملEquivalence Checking in C-based System-level Design by Sequentializing Concurrent Behaviors
In system-level designs, since many incremental refinements are applied to the designs, equivalence checking between each refinement should be applied. However, proving whether two concurrent designs are equivalent is a difficult task, not to mention that the concurrent design itself can be error-prone. In this paper, we propose an equivalence checking method for C-based descriptions of systeml...
متن کاملDesign Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation
Design optimization exploration is a key element in finding an optimal resource utilization. The exploration process applies optimizations iteratively; after applying each optimization, the result has to be validated. The research challenge for formal verification is to develop an efficient design validation flow and increase the quality of the validation. In this paper, we propose an automated...
متن کاملAutomated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs
The ever-growing complexity of digital systems has made designers move toward using Electronic System Level (ESL) design methodology at a higher abstraction level. The designs at ESL are then automatically synthesized to Register Transfer Level (RTL) by means of High Level or behavioral Synthesis (HLS) tools. Due to possibility of buggy synthesis, especially when the target design must be manip...
متن کاملFormal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation
A new approach to sequential verification of designs at different levels of abstraction by symbolic simulation is proposed. The automatic formal verification tool has been used for equivalence checking of structural descriptions at rt-level and their corresponding behavioral specifications. Gate-level results of a commercial synthesis tool have been compared to specifications at behavioral or s...
متن کامل